Field of the Invention
The present invention relates to a magnetic sensor circuit, and more specifically to a magnetic sensor circuit capable of reducing spikes generated when switching terminals of a hall element.
Background Art
Although a hall element and a signal processing circuit are included in a magnetic sensor circuit, an offset voltage occurs in the hall element or the signal processing circuit, and a voltage which is not zero is outputted even in a zero magnetic field state in which no magnetic field is applied.
As the causes of the offset voltage of the hall element, there are mentioned variations and stress in manufacturing, the influence of a peripheral magnetic field, etc. A driving method called a spinning current method is generally used for the problem of the offset voltage of the hall element.
When, in the case where terminals are respectively placed at the four corners of a square-shaped hall element, a driving current is made to flow into a 0-degrees opposite terminal and a driving current is made to flow into a 90-degrees opposite terminal, offset voltages are opposite in phase and voltages corresponding to a magnetic field become inphase when the magnetic field is applied. Therefore, signal processing is performed by adding these together and taking out a significant signal reduced in offset error.
FIG. 17 is a circuit diagram illustrating a related art twice-spinning magnetic sensor circuit.
A hall element 1 has four terminals (nodes N1 to N4) and is connected to a power supply voltage and a ground voltage through a first switch circuit 3 controlled by a first control circuit 5. A signal processing circuit 2 is connected to the hall element 1 through a second switch circuit 4 controlled by a second control circuit 6.
FIG. 18 illustrates a time chart of the related art twice-spinning magnetic sensor circuit. In the drawing, a switch is turned ON when a control signal is at a high level. The switch is turned OFF when the control signal is at a low level. One spinning period is divided into two of a period Φ1 and a period Φ2.
During the period Φ1, control signals SS1V, SS1G, SS1P, and SS1M respectively become a high level. Thus, during the period Φ1, a constant current source 15 is connected to the node N2, the ground voltage is connected to the node N4, the node N1 is connected to a positive input terminal INP, and the node N3 is connected to a negative input terminal INM.
During the period Φ2, control signals SS2V, SS2G, SS2P, and SS2M respectively become a high level. During the period Φ2, the constant current source 7 is connected to the node N3, the ground voltage is connected to the node N1, the node N2 is connected to the positive input terminal INP, and the node N4 is connected to the negative input terminal INM.
With the above connections, a differential signal (INP-INM) becomes a signal voltage Vsig corresponding to magnetism during the periods Φ1 and Φ2. Further, a negative spike-like voltage occurs during the period Φ1 immediately after switching, and a positive spike-like voltage occurs during the period Φ2.
As countermeasures for the above-described spike-like voltage errors, there are known methods disclosed in Patent Document 1 and Patent Document 2. In Patent Document 1, spike-like voltage errors generated upon clockwise and counterclockwise spinning switching are added or averaged utilizing that the spike-like voltage errors occur in positive/negative reverse sign, thereby reducing the errors. On the other hand, Patent Document 2 is based on a discrete signal processing circuit having a sample-and-hold circuit with respect to one hall element. Immediately after the spinning switching, the hall element and the signal processing circuit are separated and the signal processing circuit performs signal processing on the basis of a signal sampled and held by the sample-and-hold circuit. Therefore, signal transfer in a spike-like error period immediately after switching is masked, and the influence of the spike-like errors to signal processing accuracy is reduced.
[Patent Document 1] U.S. Pat. No. 6,927,572 Specification
[Patent Document 2] U.S. Pat. No. 5,621,319 Specification